74AUP1G07GW-Q100H Nexperia

74AUP1G07-Q100 Low-power buffer with open-drain output Rev. 3 13 January 2022 Product data sheet 1. General description The 74AUP1G07-Q100 is a single buffer with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity CMOS low power dissipation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V MM: JESD22-A115-A exceeds 200 V MIL-STD-883, method 3015 Class 3A exceeds 5000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G07GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mmNexperia 74AUP1G07-Q100 Low-power buffer with open-drain output 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G07GW-Q100 pS 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y A Y A A Y GND mna623 mna624 mna625 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G07 n.c. 1 5 V CC A 2 GND 3 4 Y 001aaf412 Fig. 4. Pin configuration SOT353-1 (TSSOP5) 6.2. Pin description Table 3. Pin description Symbol Pin Description n.c. 1 not connected A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74AUP1G07 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 3 13 January 2022 2 / 12