74AUP1G373-Q100
Low-power D-type transparent latch; 3-state
Rev. 2 27 March 2020 Product data sheet
1. General description
The 74AUP1G373-Q100 provides the single D-type transparent latch with 3-state output. While
the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW,
the latch stores the information that was present at the D-input one set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at
the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation
of input pin OE does not affect the state of the latch. Schmitt trigger action at all inputs makes the
circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V.
CC
This device ensures a very low static and dynamic power consumption across the entire V range
CC
from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I .
OFF
The I circuitry disables the output, preventing the damaging backflow current through the device
OFF
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 C to +85 C and from -40 C to +125 C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Low static power consumption; I = 0.9 A (maximum)
CC
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I circuitry provides partial Power-down mode operation
OFFNexperia
74AUP1G373-Q100
Low-power D-type transparent latch; 3-state
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP1G373GW-Q100 -40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
4. Marking
Table 2. Marking
Type number Marking code [1]
74AUP1G373GW-Q100 aW
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
D D Q Q
LE LE
3 D Q 4
1 C1
1 LE 3 4
LE
OE
EN
6
OE
6
001aae247 001aae248 001aae249
Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram
6. Pinning information
6.1. Pinning
74AUP1G373-Q100
LE 1 6 OE
GND 2 5 V
CC
3 4
D Q
aaa-009632
Fig. 4. Pin configuration SOT363 (SC-88)
74AUP1G373_Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 2 27 March 2020 2 / 17