74AUP1Z125GF,132 Nexperia

74AUP1Z125 Low-power X-tal driver with enable and internal resistor 3-state Rev. 6 11 December 2020 Product data sheet 1. General description The 74AUP1Z125 is a crystal driver with enable, internal resistor and 3-state output. When not in use the EN input can be driven HIGH, putting the device in a low power disable mode with X1 pulled HIGH via R , X2 set LOW and Y in the high impedance OFF-state. In disable mode the PU output Y assumes the high impedance OFF-state. Schmitt trigger action on the EN input makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD78B Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation at output Y OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1Z125GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1Z125GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1Z125GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1Z125GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mmNexperia 74AUP1Z125 Low-power X-tal driver with enable and internal resistor 3-state 4. Marking Table 2. Marking Type number Marking code 1 74AUP1Z125GW 55 74AUP1Z125GM 55 74AUP1Z125GN 55 74AUP1Z125GS 55 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram V CC R PU 3 6 X1 Y R bias 4 X2 1 EN 001aaf141 R = pull-up resistance. PU R = bias resistance. bias Fig. 1. Logic symbol 6. Pinning information 6.1. Pinning 74AUP1Z125 74AUP1Z125 74AUP1Z125 EN 1 6 Y EN 1 6 Y EN 1 6 Y GND 2 5 V CC GND 2 5 V CC 2 5 GND V CC X1 3 4 X2 X1 3 4 X2 001aaf144 X1 3 4 X2 001aaf143 Transparent top view 001aaf142 Transparent top view Fig. 4. Pin configuration SOT1115 Fig. 2. Pin configuration SOT363 Fig. 3. Pin configuration SOT886 and SOT1202 74AUP1Z125 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 11 December 2020 2 / 23