74AUP2G17GW Nexperia

74AUP2G17 Low-power dual Schmitt trigger Rev. 6 4 December 2012 Product data sheet 1. General description The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V and the negative voltage V is defined as the input T+ T hysteresis voltage V . H 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G17GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP2G17GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP2G17GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP2G17GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP2G17GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP2G17GW pV 74AUP2G17GM pV 74AUP2G17GF pV 74AUP2G17GN pV 74AUP2G17GS pV 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 6 161A 1Y 342A 2Y 3 4 mnb066 mnb067 Fig 1. Logic symbol Fig 2. IEC logic symbol 1A 1Y 2A 2Y mnb068 Fig 3. Logic diagram 74AUP2G17 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 4 December 2012 2 of 21