74CBTLV3384BQ,118 Nexperia

74CBTLV3384 10-bit bus switch with 5-bit output enables Rev. 4 11 February 2021 Product data sheet 1. General description The 74CBTLV3384 is a dual 5-pole, single-throw bus switch. The device features two output enable inputs (nOE) that each control five switch channels. The switches are disabled when the associated nOE input is HIGH. Schmitt-trigger action at control inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using I . The I circuitry disables the output, preventing the damaging backflow current OFF OFF through the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV3384PW -40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74CBTLV3384BQ -40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced SOT815-1 very thin quad flat package no leads 24 terminals body 3.5 5.5 0.85 mmNexperia 74CBTLV3384 10-bit bus switch with 5-bit output enables 4. Functional diagram 1A1 1A2 1A3 1A4 1A5 3 4 7 8 11 1 1OE 2 5 6 9 10 1B1 1B2 1B3 1B4 1B5 2A1 2A2 2A3 2A4 2A5 14 17 18 21 22 13 2OE nAn nBn 15 16 19 20 23 2B1 2B2 2B3 2B4 2B5 nOE 001aam095 001aai099 Fig. 1. Logic symbol Fig. 2. Logic diagram (one switch) 5. Pinning information 5.1. Pinning 74CBTLV3384 terminal 1 index area 1B1 2 23 2B5 1A1 3 22 2A5 4 21 1A2 2A4 74CBTLV3384 1B2 5 20 2B4 1B3 6 19 2B3 1OE 1 24 V CC 7 18 1A3 2A3 1B1 2 23 2B5 1A4 8 17 2A2 1A1 3 22 2A5 1B4 9 16 2B2 1A2 4 21 2A4 (1) 10 15 1B5 GND 2B1 1B2 5 20 2B4 1A5 11 14 2A1 1B3 6 19 2B3 1A3 7 18 2A3 001aam098 1A4 8 17 2A2 1B4 9 16 2B2 Transparent top view 1B5 10 15 2B1 (1) This is not a ground pin. There is no electrical or 1A5 11 14 2A1 mechanical requirement to solder the pad. In case GND 12 13 2OE soldered, the solder land should remain floating or 001aam096 connected to GND. Fig. 3. Pin configuration SOT355-1 (TSSOP24) Fig. 4. Pin configuration SOT815-1 (DHVQFN24) 74CBTLV3384 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 11 February 2021 2 / 15 GND 12 1 1OE 2OE 13 24 V CC