74HC158D.652 Nexperia

74HC158 Quad 2-input multiplexer inverting Rev. 03 12 November 2004 Product data sheet 1. General description The 74HC is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC158 is specied in compliance with JEDEC standard no. 7A. The 74HC158 is a quad 2-input multiplexer which select 4 bits of data from two sources and are controlled by a common data select input (S). The four outputs present the selected data in the inverted form. The enable input (E) is active LOW. When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74HC158. The state of S determines the particular register from which the data comes. It can also be used as a function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74HC158 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations for the output are: 1Y = E.(1l1.S + 1l0.S) 2Y = E.(2l1.S + 2l0.S) 3Y = E.(3l1.S + 3l0.S) 4Y = E.(4l1.S + 4l0.S) The 74HC158 is identical to the 74HC157 but has inverting outputs. 2. Features Low-power dissipation Inverting data path Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Multiple package options Specied from - 40 Cto+80 C and from - 40 C to +125 C.74HC158 Philips Semiconductors Quad 2-input multiplexer inverting 3. Quick reference data Table 1: Quick reference data GND = 0 V T =25 C t =t = 6 ns. amb r f Symbol Parameter Conditions Min Typ Max Unit t , t propagation delay C = 15 pF PHL PLH L V = 5 V CC nI0, nI1 to nY - 12 - ns E to nY - 14 - ns S to nY - 14 - ns C input capacitance - 3.5 - pF I 1 C power dissipation capacitance V = GND to V -40 - pF PD I CC per multiplexer 1 C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC N = number of inputs switching 2 (C V f ) = sum of outputs. L CC o 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC158N - 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HC158D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 9397 750 13805 Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 12 November 2004 2 of 16