74HC158D,652 Nexperia

74HC158 Quad 2-input multiplexer inverting Rev. 4 23 December 2015 Product data sheet 1. General description The 74HC158 is a high-speed Si-gate CMOS de vice and is pin compatible with low power Schottky TTL (LSTTL). The 74HC158 is specified in compliance with JEDEC standard no. 7A. The 74HC158 is a quad 2-input multiplexer which select 4 bits of data from two sources and are controlled by a common data select input (S). The four outputs present the selected data in the inverted form. The enable input (E) is active LOW. When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74HC158. The state of S determines the particular register from which the data comes. It can also be used as a function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74HC158 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations for the output are: 1Y = E.(1l1.S 1l0.S) 2Y = E.(2l1.S 2l0.S) 3Y = E.(3l1.S 3l0.S) 4Y = E.(4l1.S 4l0.S) The 74HC158 is identical to the 74HC157 but has inverting outputs. 2. Features and benefits Low-power dissipation Inverting data path Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 74HC158 Nexperia Quad 2-input multiplexer inverting 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC158D 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 4. Functional diagram 2 3 5 6 11 10 14 13 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 1 S MULTIPLEXER 15 E OUTPUTS 1Y 2Y 3Y 4Y 4 7 9 12 E DD Fig 1. Functional diagram 1 G1 15 EN 1 S 2 2 MUX 1I0 1 4 4 1Y 3 3 1I1 1 5 2I0 5 7 2Y 6 7 2I1 6 11 3I0 9 3Y 14 10 3I1 12 14 13 4I0 12 4Y 13 11 4I1 9 15 E 10 DDE Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC158 All information provided in this document is subject to legal disclaimers Product data sheet Rev. 4 23 December 2015 2 of 16 Nexperia B.V. 2017. All rights reserved DDE