74HC160PW,118 NXP

74HC160 Presettable synchronous BCD decade counter asynchronous reset Rev. 4 27 March 2019 Product data sheet 1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive- going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC160D -40 C to +125 C SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1Nexperia 74HC160 Presettable synchronous BCD decade counter asynchronous reset 4. Functional diagram 3 4 5 6 D0 D1 D2 D3 9 3 4 5 6 9 PE PARALLEL PE D0 D1 D2 D3 LOAD CIRCUITRY 7 CEP 10 CET 10 CET TC 15 2 CP 7 CEP D TC 15 INH DECADE 1 MR 2 CP CP COUNTER Q0 Q1 Q2 Q3 1 MR R D Q0 Q1 Q2 Q3 14 13 12 11 14 13 12 11 aaa-024737 aaa-012184 Fig. 1. Functional diagram Fig. 2. Logic symbol CTRDIV10 1 R 9 M1 7 G3 10 G4 2 C2/1,3,4+ 14 3 1,2D 13 4 12 5 6 11 15 4CT = 9 aaa-024738 Fig. 3. IEC logic symbol 74HC160 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 4 27 March 2019 2 / 15