74HC173PW,112 Nexperia

74HC173 74HCT173 Quad D-type flip-flop positive-edge trigger 3-state Rev. 4 25 January 2021 Product data sheet 1. General description The 74HC173 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC173: CMOS level For 74HCT173: TTL level Gated input enable for hold (do nothing) mode Gated output enable control mode Edge-triggered D-type register Asynchronous master reset ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC173D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT173D 74HC173PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mmNexperia 74HC173 74HCT173 Quad D-type flip-flop positive-edge trigger 3-state 4. Functional diagram 7 CP 14 D0 Q0 3 13 D1 Q1 4 FF1 to 12 D2 Q2 5 & 9 FF4 10 11 D3 Q3 6 C1 7 1 & 14 13 12 11 EN 2 9 E1 15 D0 D1 D2 D3 9 E1 R 10 E2 10 E2 14 3 7 CP 1D 15 MR 1 OE1 13 4 2 OE2 1 OE1 MR Q0 Q1 Q2 Q3 12 5 2 OE2 11 6 15 3 4 5 6 aaa-024783 aaa-024784 aaa-024785 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol D0 D1 D2 D3 E1 E2 FF FF FF FF D Q D Q D Q D Q 1 2 3 4 CP CP Q CP Q CP Q CP Q RD RD RD RD MR OE1 OE2 Q0 Q1 Q2 Q3 aaa-024786 Fig. 4. Logic diagram 74HC HCT173 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 25 January 2021 2 / 17