74HC175PW-Q100J Nexperia

74HC175-Q100 74HCT175-Q100 Quad D-type flip-flop with reset positive-edge trigger Rev. 2 4 February 2021 Product data sheet 1. General description The 74HC175-Q100 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Input levels: For 74HC175-Q100: CMOS level For 74HCT175-Q100: TTL level Four edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC175D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT175D-Q100 74HC175PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT175PW-Q100Nexperia 74HC175-Q100 74HCT175-Q100 Quad D-type flip-flop with reset positive-edge trigger 4. Functional diagram 9 C1 1 R 9 2 2 CP Q0 4 4 1D D0 3 3 Q0 7 7 Q1 5 5 D1 6 6 Q1 10 Q2 12 10 D2 11 12 Q2 11 15 Q3 13 D3 15 14 Q3 13 MR 14 1 aaa-008921 aaa-008922 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 D1 D2 D3 D Q D Q D Q D Q FF1 FF2 FF3 FF4 CP CP CP CP Q Q Q Q RD RD RD RD CP MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 aaa-008927 Fig. 3. Logic diagram 74HC HCT175 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 4 February 2021 2 / 16