74HC574D/SPLITREEL NXP

74HC574; 74HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 4 March 2016 Product data sheet 1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Input levels: For 74HC574: CMOS level For 74HCT574: TTL level 3-state non-inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input Complies with JEDEC standard no. 7 A Multiple package options ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC574D 40 C to +125 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74HCT574D 74HC574DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74HCT574DB 74HC574PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74HCT574PW74HC574; 74HCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 4. Functional diagram      ( 7 $ 67  WR  3 6      DPQ Fig 1. Functional diagram ' ' ' ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4 ' 4  )) )) ))  )) )) ))  )) ))  Fig 2. Logic diagram 74HC_HCT574 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 4 March 2016 2 of 18 DDK 4 4 4 4 4 4 4 4 2( &3 &3 &3 &3 &3 &3 &3 &3 &3 ' ' ' ' ' 2( &3   4 '  4 '  4 ' ))  87287 4 '   4 )) '  4 '  4 '  4 '