74HC174N,652 NXP

74HC174 74HCT174 Hex D-type flip-flop with reset positive-edge trigger Rev. 3 16 April 2013 Product data sheet 1. General description The 74HC174 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Input levels: For 74HC174: CMOS level For 74HCT174: TTL level Six edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from 40 C to +85 C and 40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HCT174N 74HC174D 40 C to +125 C SO16 plastic small outline package 16 leads body width SOT109-1 3.9 mm 74HCT174D 74HC174DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74HCT174DB 74HC174PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT174PW74HC174 74HCT174 NXP Semiconductors Hex D-type flip-flop with reset positive-edge trigger 4. Functional diagram Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74HC HCT174 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 16 April 2013 2 of 18