74F374 Octal D-Type Flip-Flop with 3-STATE Outputs May 1988 Revised September 2000 74F374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The 74F374 is a high-speed, low-power octal D-type flip- Edge-triggered D-type inputs flop featuring separate D-type inputs for each flip-flop and Buffered positive edge-triggered clock 3-STATE outputs for bus-oriented applications. A buffered 3-STATE outputs for bus-oriented applications Clock (CP) and Output Enable (OE) are common to all flip- Guaranteed 4000V minimum ESD protection flops. Ordering Code: Order Number Package Number Package Description 74F374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009524 www.fairchildsemi.comUnit Loading/Fan Out U.L. Input I /I IH IL Pin Names Description Output I /I HIGH/LOW OH OL D D Data Inputs 1.0/1.0 20 A/0.6 mA 0 7 CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 A/0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 A/0.6 mA O O 3-STATE Outputs 150/40 (33.3) 3 mA/24 mA (20 mA) 0 7 Functional Description Truth Table The 74F374 consists of eight edge-triggered flip-flops with Inputs Internal Output individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to D O CP OE Register n n all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time H LH H requirements on the LOW-to-HIGH Clock (CP) transition. L LL L With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is XX H X Z HIGH, the outputs go to the high impedance state. Opera- H = HIGH Voltage Level tion of the OE input does not affected the state of the flip- L = LOW Voltage Level flops. X = Immaterial Z = High Impedance = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F374