74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
April 1988
Revised October 2000
74F675A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description Features
The 74F675A contains a 16-bit serial in/serial out shift reg- Serial-to-parallel converter
ister and a 16-bit parallel out storage register. Separate
16-Bit serial I/O shift register
serial input and output pins are provided for expansion to
16-Bit parallel out storage register
longer words. By means of a separate clock, the contents
Recirculating parallel transfer
of the shift register are transferred to the storage register.
The contents of the storage register can also be loaded Expandable for longer words
back into the shift register. A HIGH signal on the Chip
Slim 24 lead package
Select input prevents both shifting and parallel loading.
74F675A version prevents false clocking through
CS or R/W inputs
Ordering Code:
Order Number Package Number Package Description
74F675ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F675APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
74F675ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
2000 Fairchild Semiconductor Corporation DS009587 www.fairchildsemi.comUnit Loading/Fan Out
U.L. Input I /I
IH IL
Pin Names Description
Output I /I
HIGH/LOW
OH OL
SI Serial Data Input 1.0/1.0 20 A/0.6 mA
CS Chip Select Input (Active LOW) 1.0/1.0 20 A/0.6 mA
SHCP Shift Clock Pulse Input (Active Falling Edge) 1.0/1.0 20 A/0.6 mA
STCP Store Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 A/0.6 mA
R/W Read/Write Input 1.0/1.0 20 A/0.6 mA
SO Serial Data Output 50/33.3 1 mA/20 mA
Q Q Parallel Data Outputs 50/33.3 1 mA/20 mA
0 15
Functional Description
The 16-Bit shift register operates in one of four modes, as The storage register is in the Hold mode when either CS or
determined by the signals applied to the Chip Select (CS), R/W is HIGH. With CS and R/W both LOW, the storage
Read/Write (R/W) and Store Clock Pulse (STCP) input. register is parallel loaded from the shift register on the ris-
State changes are indicated by the falling edge of the Shift ing edge of STCP.
Clock Pulse (SHCP). In the Shift Right mode, data enters
To prevent false clocking of the shift register, SHCP should
D from the Serial Input (SI) pin and exits from Q via the
0 15 be in the LOW state during a LOW-to-HIGH transition of
Serial Data Output (SO) pin. In the Parallel Load mode,
CS. To prevent false clocking of the storage register, STCP
data from the storage register outputs enter the shift regis- should be LOW during a HIGH-to-LOW transition of CS if
ter and serial shifting is inhibited.
R/W is LOW, and should also be LOW during a
HIGH-to-LOW transition of R/W if CS is LOW.
Shift Register Operations Table Storage Register Operations Table
Control Inputs Operating Inputs Operating
CS R/W SHCP STCP Mode CS R/W STCP Mode
H X X X Hold HX X Hold
LL X Shift Right LH X Hold
LH L Shift Right LL Parallel Load
H = HIGH Voltage Level
LH H Parallel Load,
L = LOW Voltage Level
No Shifting
X = Immaterial
= HIGH-to-LOW Transition
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F675A