74F273 Octal D-Type Flip-Flop April 1988 Revised September 2000 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D-type flip-flops with Ideal buffer for MOS microprocessor or memory individual D inputs and Q outputs. The common buffered Eight edge-triggered D-type flip-flops Clock (CP) and Master Reset (MR) inputs load and reset Buffered common clock (clear) all flip-flops simultaneously. Buffered, asynchronous Master Reset The register is fully edge-triggered. The state of each D See 74F377 for clock enable version input, one setup time before the LOW-to-HIGH clock transi- See 74F373 for transparent latch version tion, is transferred to the corresponding flip-flops Q output. All outputs will be forced LOW independently of Clock or See 74F374 for 3-STATE version Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Ordering Code: Order Number Package Number Package Description 74F273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009511 www.fairchildsemi.comUnit Loading/Fan Out U.L. Input I /I IH IL Pin Names Description Output I /I HIGH/LOW OH OL D D Data Inputs 1.0/1.0 20 A/0.6 mA 0 7 MR Master Reset (Active LOW) 1.0/1.0 20 A/0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 A/0.6 mA Q Q Data Outputs 50/33.3 1 mA/20 mA 0 7 Mode Select-Function Table Inputs Output Operating Mode MR CP D Q n n Reset (Clear) L X X L Load 1 H hH Load 0 H lL H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial = LOW-to-HIGH clock transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F273