74HC237-Q100 3-to-8 line decoder, demultiplexer with address latches Rev. 2 26 October 2021 Product data sheet 1. General description The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC237D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mmNexperia 74HC237-Q100 3-to-8 line decoder, demultiplexer with address latches 4. Functional diagram 4 LE Y0 15 Y1 14 Y2 13 A0 1 Y3 12 2 A1 INPUT 3 TO 8 Y4 11 LATCHES DECODER 3 A2 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab871 Fig. 1. Functional diagram DX 4 15 C8 0 1 14 0 1 2 0 13 8D,G 2 7 3 12 3 2 11 4 10 5 5 9 & 6 4 7 6 7 LE 15 Y0 14 X/Y Y1 13 4 15 Y2 C8 0 1 A0 12 1 14 Y3 8D,1 1 2 INPUT 3 TO 8 A1 11 2 13 LATCHES DECODER Y4 8D,2 2 3 A2 10 3 12 Y5 8D,4 3 9 11 Y6 4 7 10 Y7 5 5 9 & 6 6 7 E1 7 5 001aab869 EN 6 E2 001aab870 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC237 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 26 October 2021 2 / 14