74HC237N,652 NXP

74HC237 3-to-8 line decoder, demultiplexer with address latches Rev. 6 23 August 2012 Product data sheet 1. General description The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A. The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus-oriented systems. 2. Features and benefits Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Low-power dissipation ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC237N 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74HC237D 40 C to +125 C SO16 plastic small outline package 16 leads body width SOT109-1 3.9 mm 74HC237DB 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm74HC237 NXP Semiconductors 3-to-8 line decoder, demultiplexer with address latches 4. Functional diagram 4 LE Y0 15 Y1 14 Y2 13 1 A0 Y3 12 2 A1 INPUT 3 TO 8 Y4 11 LATCHES DECODER 3 A2 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab871 Fig 1. Functional diagram DX 4 15 C8 0 1 14 0 1 0 2 13 8D,G 2 7 3 12 4 2 3 11 LE 4 10 15 Y0 5 14 5 9 Y1 & 6 13 6 7 Y2 7 1 A0 12 Y3 2 INPUT 3 TO 8 A1 11 LATCHES DECODER Y4 3 A2 10 X/Y Y5 9 4 15 C8 0 Y6 1 7 14 1 8D,1 Y7 2 13 8D,2 2 3 12 8D,4 3 E1 11 5 001aab869 4 6 10 5 E2 5 9 & 6 6 7 7 EN 001aab870 Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC237 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 23 August 2012 2 of 17