74HC4052D-Q100,118 NXP

74HC4052-Q100 74HCT4052-Q100 Dual 4-channel analog multiplexer/demultiplexer Rev. 2 22 November 2012 Product data sheet 1. General description The 74HC4052-Q100 74HCT4052-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC standard no. 7A. The 74HC4052-Q100 74HCT4052-Q100 is a dual 4-channel analog multiplexer/demultiplexer with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1. V and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E). CC The V to GND ranges are 2.0 V to 10.0 V for the 74HC4052-Q100, and 4.5 V to 5.5 V CC for the 74HCT4052-Q100. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between V as a positive limit and V as a negative limit. V V may not exceed CC EE CC EE 10.0 V. For operation as a digital multiplexer/demultiplexer, V is connected to GND EE (typically ground). This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide analog input voltage range from 5 V to +5 V Low ON resistance: 80 (typical) at V V =4.5 V CC EE 70 (typical) at V V =6.0 V CC EE 60 (typical) at V V =9.0 V CC EE Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical break before make built-in ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) CDM AEC-Q100-011 revision B exceeds 1000 V Multiple package options74HC4052-Q100 74HCT4052-Q100 Nexperia Dual 4-channel analog multiplexer/demultiplexer 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4052D-Q100 40 C to +125 C SO16 plastic small outline package 16 leads body SOT109-1 width 3.9 mm 74HCT4052D-Q100 74HC4052PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT4052PW-Q100 74HC4052BQ-Q100 40 C to +125 C DHVQFN16 plastic dual-in line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT4052BQ-Q100 body 2.5 3.5 0.85 mm 5. Functional diagram 10 0 0 4 3 9 1 13 6 G4 1Z 1Y0 12 MDX 10 S0 1Y1 14 0 1 9 S1 1Y2 15 1 5 3 1Y3 11 2 2 2Y0 1 3 4 2Y1 5 12 2Y2 2 14 13 6 E 2Y3 4 15 2Z 11 001aah824 3 001aah825 Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC HCT4052 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 22 November 2012 2 of 26