INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT390 Dual decade ripple counter December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Dual decade ripple counter 74HC/HCT390 FEATURES decade or bi-quinary configuration, since they share a common master reset input (nMR). If the two master reset Two BCD decade or bi-quinary counters inputs (1MR and 2MR) are used to simultaneously clear all One package can be configured to divide-by-2, 4, 5, 10, 8 bits of the counter, a number of counting configurations 20, 25, 50 or 100 are possible within one package. The separate clocks (nCP and nCP ) of each section allow ripple counter or Two master reset inputs to clear each decade counter 0 1 frequency division applications of divide-by-2, 4, 5, 10, 20, individually 25, 50 or 100. Output capability: standard Each section is triggered by the HIGH-to-LOW transition of I category: MSI CC the clock inputs (nCP and nCP ). For BCD decade 0 1 operation, the nQ output is connected to the nCP input 0 1 GENERAL DESCRIPTION of, the divide-by-5 section. For bi-quinary decade operation, the nQ output is connected to the nCP input 3 0 The 74HC/HCT390 are high-speed Si-gate CMOS devices and nQ becomes the decade output. 0 and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC The master reset inputs (1MR and 2MR) are active HIGH standard no. 7A. asynchronous inputs to each decade counter which operates on the portion of the counter identified by the 1 The 74HC/HCT390 are dual 4-bit decade ripple counters and 2 prefixes in the pin configuration. A HIGH level on divided into four separately clocked sections. The counters the nMR input overrides the clocks and sets the four have two divide-by-2 sections and two divide-by-5 outputs LOW. sections. These sections are normally used in a BCD QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5V PHL PLH L CC nCP to nQ 14 18 ns 0 0 nCP to nQ 15 19 ns 1 1 nCP to nQ 23 26 ns 1 2 nCP to nQ 15 19 ns 1 3 nMR to Q 16 18 ns n f maximum clock frequency nCP ,nCP 66 61 MHz max 0 1 C input capacitance 3.5 3.5 pF I C power dissipation capacitance per counter notes 1 and 2 20 21 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC December 1990 2