74HC3G07-Q100 74HCT3G07-Q100 Triple buffer with open-drain outputs Rev. 3 24 January 2019 Product data sheet 1. General description The 74HC3G07-Q100 74HCT3G07-Q100 is a triple buffer with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Input levels: For 74HC3G07-Q100: CMOS level For 74HCT3G07-Q100: TTL level Complies with JEDEC standard no. 7 A Wide supply voltage range from 2.0 V to 6.0 V High noise immunity Low power dissipation Balanced propagation delays ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC3G07DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74HCT3G07DP-Q100 74HC3G07DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74HCT3G07DC-Q100Nexperia 74HC3G07-Q100 74HCT3G07-Q100 Triple buffer with open-drain outputs 4. Marking Table 2. Marking code Type number Marking code 1 74HC3G07DP-Q100 H07 74HCT3G07DP-Q100 T07 74HC3G07DC-Q100 H07 74HCT3G07DC-Q100 T07 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1A 1Y 1 2A 2Y 2A 2Y Y 3A 3Y 1 3A 3Y A 001aah762 001aah763 GND mna591 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one buffer) 6. Pinning information 6.1. Pinning 74HC3G07-Q100 74HCT3G07-Q100 1A 1 8 V CC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y aaa-009065 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 6 data input GND 4 ground (0 V) 1Y, 2Y, 3Y 7, 5, 2 data output V 8 supply voltage CC 74HC HCT3G07 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 24 January 2019 2 / 12