74HC4050D Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC4050 Hex high-to-low level shifter December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Hex high-to-low level shifter 74HC4050 FEATURES therefore be used. This feature enables the non-inverting buffers to be used as logic level translators, which will Output capability: standard convert high level logic to low level logic, while operating I category: SSI CC from a low voltage power supply. For example 15 V logic (4000B series) can be converted down to 2 V logic. GENERAL DESCRIPTION The actual input switch level remains related to the V CC and is the same as mentioned in the family characteristics. The 74HC4050 is a high-speed Si-gate CMOS device and is pin compatible with the 4050 of the 4000B series. It is specified in compliance with JEDEC standard no. 7A. APPLICATIONS The 74HC4050 provides six non-inverting buffers with a Converting 15 V logic (4000B series) down to 2 V logic. modified input protection structure, which has no diode connected to V . Input voltages of up to 15 V may CC QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC t / t propagation delay nA to nY C = 15 pF V = 5 V 7 ns PHL PLH L CC C input capacitance 3.5 pF I C power dissipation capacitance per buffer note 1 14 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC 2 (C V f ) = sum of outputs L CC o ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2