74HCT2G125DP-Q100H Nexperia

74HC2G125-Q100; 74HCT2G125-Q100 Dual buffer/line driver; 3-state Rev. 2 1 November 2018 Product data sheet 1. General description The 74HC2G125-Q100; 74HC2G125-Q100 are dual buffer/line drivers with 3-state outputs controlled by the output enable inputs (nOE). Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC2G125-Q100: CMOS level For 74HCT2G125-Q100: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G125DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 body width 3 mm; lead length 0.5 mm 74HCT2G125DP-Q100 74HC2G125DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package; SOT765-1 8 leads; body width 2.3 mm 74HCT2G125DC-Q100Nexperia 74HC2G125-Q100; 74HCT2G125-Q100 Dual buffer/line driver; 3-state 4. Marking Table 2. Marking codes Type number Marking code[1] 74HC2G125DP-Q100 H25 74HCT2G125DP-Q100 T25 74HC2G125DC-Q100 H25 74HCT2G125DC-Q100 T25 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 1A 1Y 6 2 1 1OE 6 1 1 EN1 5 2A 2Y 3 Y A 5 3 2 7 2OE 7 EN2 OE mce185 mce186 mna120 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one driver) 6. Pinning information 6.1. Pinning 74HC2G125 74HCT2G125 1OE 1 8 V CC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 001aae074 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1OE, 2OE 1, 7 output enable input (active LOW) 1A, 2A 2, 5 data input GND 4 ground (0 V) 1Y, 2Y 6, 3 data output V 8 supply voltage CC 74HC_HCT2G125_Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 2 1 November 2018 2 / 13