74HCT2G34GW,125 Nexperia

74HC2G34 74HCT2G34 Dual buffer gate Rev. 01 6 October 2006 Product data sheet 1. General description The 74HC2G34 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34 74HCT2G34 provides two buffers. 2. Features n Wide supply voltage range from 2.0 V to 6.0 V n Complies with JEDEC standard no. 7A n High noise immunity n ESD protection: u HBM JESD22-A114-D exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Low power dissipation n Balanced propagation delays n Unlimited input rise and fall times n Multiple package options n Specied from 40- Cto+85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G34GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74HC2G34GV 40- C to +125 C SC-74 plastic surface-mounted package (TSOP6) 6 leads SOT457 74HCT2G34GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74HCT2G34GV -40 C to +125 C SC-74 plastic surface-mounted package (TSOP6) 6 leads SOT457 4. Marking Table 2. Marking Type number Marking code 74HC2G34GW PA 74HC2G34GV P34 74HCT2G34GW UA 74HCT2G34GV U3474HC2G34 74HCT2G34 Nexperia Dual buffer gate 5. Functional diagram 1 161A 1Y 1 6 342A 2Y 1 3 4 A Y mnb064 001aac536 mnb063 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74HC2G34 74HCT2G34 1A 1 6 1Y GND 2 5 V CC 2A 3 4 2Y 001aaf303 Fig 4. Pin conguration 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output V 5 supply voltage CC 1Y 6 data output 74HC HCT2G34 1 Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 01 6 October 2006 2 of 14