Product Information

74HCT74D-Q100,118

74HCT74D-Q100,118 electronic component of Nexperia

Datasheet
NXP Semiconductors Flip Flops

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.4817 ea
Line Total: USD 0.48

4658 - Global Stock
Ships to you between
Thu. 30 May to Mon. 03 Jun
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
4649 - WHS 1


Ships to you between Thu. 30 May to Mon. 03 Jun

MOQ : 1
Multiples : 1
1 : USD 0.4817
10 : USD 0.3464
100 : USD 0.2409
1000 : USD 0.1732
2500 : USD 0.1519
10000 : USD 0.1448
25000 : USD 0.1388
50000 : USD 0.1376

     
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RoHS - XON
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74HC74-Q100 74HCT74-Q100 Dual D-type flip-flop with set and reset positive edge-trigger Rev. 4 21 April 2020 Product data sheet 1. General description The 74HC74-Q100 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Input levels: For 74HC74-Q100: CMOS level For 74HCT74-Q100: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC74D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT74D-Q100 74HC74PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT74PW-Q100 74HC74BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74HCT74BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74HC74-Q100 74HCT74-Q100 Dual D-type flip-flop with set and reset positive edge-trigger 4. Functional diagram 1SD 4 SD 1Q 1D 2 Q D 5 1CP 3 CP FF 1Q Q 6 RD 4 4 10 S 5 1RD 3 1 C1 1SD 2SD 2 2SD 1D 6 10 SD 1 2 1D 1Q 5 R D Q 12 2D 2Q 9 SD 2Q 2D 3 1CP 12 D Q 9 CP 10 11 2CP FF S 9 2CP 1Q 6 11 CP 11 Q C1 8 FF 2Q 2Q 12 RD Q 8 1D 8 13 RD 1RD 2RD R 2RD 1 13 mna420 mna418 mna419 13 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Functional diagram Q C C C C C C D Q C C RD SD mna421 CP C C Fig. 4. Logic diagram for one flip-flop 74HC HCT74 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 4 21 April 2020 2 / 17

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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