74HCT74PW,112 Nexperia

74HC74 74HCT74 Dual D-type flip-flop with set and reset positive edge-trigger Rev. 7 13 September 2021 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC74: CMOS level For 74HCT74: TTL level Symmetrical output impedance High noise immunity Balanced propagation delays Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC74D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT74D 74HC74PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT74PW 74HC74BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals 74HCT74BQ body 2.5 3 0.85 mmNexperia 74HC74 74HCT74 Dual D-type flip-flop with set and reset positive edge-trigger 4. Functional diagram 1SD 4 SD 1Q 1D 2 Q D 5 1CP 3 CP FF 1Q Q 6 RD 4 4 10 S 5 1RD 3 1 C1 1SD 2SD 2 2SD 1D 6 10 SD 1 2 1D 1Q 5 R D Q 12 2D 2Q 9 SD 2Q 2D 3 1CP 12 D Q 9 CP 10 11 2CP FF S 9 2CP 1Q 6 11 CP 11 Q C1 8 FF 2Q 2Q 12 RD Q 8 1D 8 13 RD 1RD 2RD R 2RD 1 13 mna420 mna418 mna419 13 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Functional diagram Q C C C C C C D Q C C RD SD mna421 CP C C Fig. 4. Logic diagram for one flip-flop 74HC HCT74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 13 September 2021 2 / 17