74LVC00A Quad 2-input NAND gate Rev. 7 25 April 2012 Product data sheet 1. General description The 74LVC00A provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC00AD 40 Cto +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC00ADB 40 Cto +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LVC00APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC00ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm74LVC00A Nexperia Quad 2-input NAND gate 4. Functional diagram 1 & 3 1 1A 2 1Y 3 2 1B 4 4 2A & 6 2Y 6 5 5 2B 9 9 3A 3Y 8 & 8 10 3B 10 A 12 4A 12 4Y 11 Y 13 4B & 11 13 B mna212 mna246 mna211 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning terminal 1 index area 2 13 1B 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 2A 4 00 11 4Y 1Y 3 12 4A 2A 4 00 11 4Y 2B 5 (1) 10 3B GND 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y 001aac939 001aac938 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8,11 data output GND 7 ground (0 V) V 14 supply voltage CC 74LVC00A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 25 April 2012 2 of 14 GND 7 1 1A 8 14 3Y V CC