74LV32PW,118 NXP

74LV32 Quad 2-input OR gate Rev. 03 9 November 2007 Product data sheet 1. General description The 74LV32 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32. The 74LV32 provides a quad 2-input OR function. 2. Features Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV32N - 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74LV32D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV32DB - 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV32PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LV32BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 2.5 3 0.85 mm74LV32 NXP Semiconductors Quad 2-input OR gate 4. Functional diagram 1 1 3 2 4 1 1 1A 6 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B 1 8 10 9 3A 3Y 8 10 3B A 12 4A 12 4Y 11 1 11 Y 13 4B 13 B mna241 mna242 mna243 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74LV32 terminal 1 index area 74LV32 1B 2 13 4B 1A 1 14 V 1Y 3 12 4A CC 1B 2 13 4B 4 11 2A 4Y 1Y 3 12 4A 2B 5 (1) 10 3B V CC 2A 4 11 4Y 2Y 6 9 3A 2B 5 10 3B 2Y 6 9 3A 001aah105 GND 7 8 3Y Transparent top view 001aah104 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration DIP14, SO14 and (T)SSOP14 Fig 5. Pin conguration DHVQFN14 74LV32 3 NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 9 November 2007 2 of 15 7 1 GND 1A 3Y 8 14 V CC