INTEGRATED CIRCUITS 74LV373 Octal D-type transparent latch (3-State) Product specification 1998 Jun 10 Supersedes data of 1997 March 04 IC24 Data Handbook Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74LV373 FEATURES DESCRIPTION The 74LV373 is a low-voltage Si-gate CMOS device that is pin and Wide operating voltage: 1.0 to 5.5V function compatible with 74HC/HCT373. Optimized for Low Voltage applications: 1.0V to 3.6V The 74LV373 is an octal D-type transparent latch featuring separate Accepts TTL input levels between V = 2.7V and V = 3.6V D-type inputs for each latch and 3-State outputs for bus oriented CC CC applications. A latch enable (LE) input and an output enable (OE) Typical V (output ground bounce) < 0.8V at V = 3.3V, OLP CC input are common to all internal latches. T = 25C amb The 373 consists of eight D-type transparent latches with 3-State Typical V (output V undershoot) > 2V at V = 3.3V, OHV OH CC true outputs. When LE is HIGH, data at the Dn inputs enters the T = 25C amb latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. Common 3-State output enable input When LE is LOW the latches store the information that was present Output capability: bus driver at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are I category: MSI CC available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 373 is functionally identical to the 573, but the 573 has a different pin arrangement. QUICK REFERENCE DATA GND = 0V T = 25C t = t 2.5 ns amb r f SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay C = 15pF L t /t D to Q V = 3.3V 10 ns n n CC PHL PLH LE to Q 12 n C Input capacitance 3.5 pF I C Power dissipation capacitance per latch Notes 1, 2 22 pF PD NOTES: 1. C is used to determine the dynamic power dissipation (P in W) PD D 2 2 P = C V x f (C V f ) where: D PD CC i L CC o f = input frequency in MHz C = output load capacity in pF i L f = output frequency in MHz V = supply voltage in V o CC 2 (C V f ) = sum of the outputs. L CC o 2. The condition is V = GND to V I CC. ORDERING AND PACKAGE INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. 20-Pin Plastic DIL 40C to +125C 74LV373 N 74LV373 N SOT146-1 20-Pin Plastic SO 40C to +125C 74LV373 D 74LV373 D SOT163-1 20-Pin Plastic SSOP Type II 40C to +125C 74LV373 DB 74LV373 DB SOT339-1 20-Pin Plastic TSSOP Type I 40C to +125C 74LV373 PW 74LV373PW DH SOT360-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enabled input (active LOW) 2, 5, 6, 9, 12, Q Q 3-State latch outputs 0 7 15, 16, 19 3, 4, 7, 8, 13, D D Data inputs 0 7 14, 17, 18 10 GND Ground (0V) 11 LE Latch enable input (active HIGH) 20 V Positive supply voltage CC 2 1998 Jun 10 8531934 19545