74LVC06A-Q100 Hex inverter with open-drain outputs Rev. 3 4 August 2020 Product data sheet 1. General description The 74LVC06A-Q100 provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C 5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC06AD-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC06APW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC06ABQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC06A-Q100 Hex inverter with open-drain outputs 4. Functional diagram 1 1 2 1A 1Y 1 1A 1Y 2 1 3 4 3 2A 2Y 4 2A 2Y 1 5 5 3A 3Y 6 6 3A 3Y 9 4A 4Y 8 9 1 8 4A 4Y 11 5A 5Y 10 11 1 10 5A 5Y Y 13 6A 6Y 12 13 1 12 A 6A 6Y GND mna525 mna526 mna527 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram for one gate 5. Pinning information 5.1. Pinning 74LVC06A-Q100 terminal 1 index area 74LVC06A-Q100 1Y 2 13 6A 2A 3 12 6Y 1A 1 14 V CC 2Y 4 11 5A 1Y 2 13 6A 5 10 3A (1) 5Y GND 2A 3 12 6Y 3Y 6 9 4A 4 11 2Y 5A 3A 5 10 5Y aaa-007302 Transparent top view 3Y 6 9 4A (1) This is not a ground pin. There is no electrical or GND 7 8 4Y mechanical requirement to solder the pad. In case aaa-007301 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input 1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output GND 7 ground (0 V) V 14 supply voltage CC 74LVC06A Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 4 August 2020 2 / 12 GND 7 1 1A 4Y 8 14 V CC