74LVC126APW,112 Nexperia

74LVC126A Quad buffer/line driver with 5 V tolerant input/outputs 3-state Rev. 11 20 September 2021 Product data sheet 1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC126AD -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC126APW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC126ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC126A Quad buffer/line driver with 5 V tolerant input/outputs 3-state 4. Functional diagram 2 1A 1Y 3 2 1 3 1 1OE 1 EN1 2A 2Y 6 5 5 6 4 2OE 4 9 3A 3Y 8 9 8 3OE 10 10 4A 4Y 12 11 12 11 13 4OE 13 mna235 mna236 Fig. 1. Logic symbol Fig. 2. IEC logic symbol nA nY nOE mna234 Fig. 3. Logic diagram 5. Pinning information 5.1. Pinning 74LVC126A terminal 1 index area 74LVC126A 1A 2 13 4OE 3 12 1 14 1Y 4A 1OE V CC 2OE 4 11 4Y 1A 2 13 4OE 2A 5 (1) 10 3OE GND 1Y 3 12 4A 2Y 6 9 3A 2OE 4 11 4Y 2A 5 10 3OE 001aac983 Transparent top view 6 9 2Y 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case aaa-012622 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74LVC126A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 20 September 2021 2 / 13 GND 7 1 1OE 3Y 8 14 V CC