74LVC16240ADGG,118 Nexperia

74LVC16240A 16-bit buffer/line driver with 5V tolerant inputs/outputs inverting 3-state Rev. 5 25 April 2019 Product data sheet 1. General description The 74LVC16240A is a 16-bit inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and from -40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC16240ADGG -40 C to +125 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mmNexperia 74LVC16240A 16-bit buffer/line driver with 5V tolerant inputs/outputs inverting 3-state 4. Functional diagram 47 36 2 13 1A0 1Y0 3A0 3Y0 46 35 3 14 1A1 1Y1 3A1 3Y1 44 5 33 16 1A2 1Y2 3A2 3Y2 43 6 32 17 1A3 1Y3 3A3 3Y3 1 25 1OE 3OE 41 30 8 19 2A0 2Y0 4A0 4Y0 40 9 29 20 2A1 2Y1 4A1 4Y1 38 11 27 22 2A2 2Y2 4A2 4Y2 37 12 26 23 2A3 2Y3 4A3 4Y3 48 24 2OE 4OE 001aaa439 Fig. 1. Logic symbol 1 1OE 1EN 48 2EN 2OE 25 3OE 3EN 24 4OE 4EN 47 2 1A0 1 1 1Y0 3 46 1A1 1Y1 5 44 1A2 1Y2 6 43 1A3 1Y3 41 8 2A0 2Y0 1 2 40 9 2A1 2Y1 38 11 2A2 2Y2 12 37 2A3 2Y3 36 13 3A0 3Y0 1 3 35 14 3A1 3Y1 33 16 3A2 3Y2 32 17 3A3 3Y3 30 19 4A0 1 4 4Y0 29 20 4A1 4Y1 27 22 4A2 4Y2 26 23 4A3 4Y3 001aaa442 Fig. 2. IEC logic symbol 74LVC16240A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 5 25 April 2019 2 / 12