74LVC16241ADGG,118 Nexperia

74LVC16241A 16-bit buffer/line driver with 5 V tolerant inputs/outputs 3-state Rev. 5 26 April 2019 Product data sheet 1. General description The 74LVC16241A is a 16-bit non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs (1OE, 2OE, 3OE and 4OE). Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs and outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels High-impedance outputs when V = 0 V CC Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC16241ADGG -40 C to +125 C TSSOP48 plastic thin shrink small outline package 48 leads SOT362-1 body width 6.1 mmNexperia 74LVC16241A 16-bit buffer/line driver with 5 V tolerant inputs/outputs 3-state 4. Functional diagram 1 1 25 1OE 1EN 48 2EN 2OE 1OE 3OE 25 3OE 3EN 2 47 1A0 1Y0 24 4OE 4EN 1A1 1Y1 3 46 47 2 44 5 1A0 1D 1 1Y0 1A2 1Y2 3 46 6 1A1 1Y1 43 1A3 1Y3 5 44 41 2A0 2Y0 1A2 1Y2 8 6 43 1A3 1Y3 40 2A1 2Y1 9 41 8 2A0 2Y0 38 2A2 2Y2 11 2D 2 40 9 2A1 2A3 2Y3 12 2Y1 37 38 11 2A2 36 3A0 3Y0 13 2Y2 12 37 3A1 3Y1 2A3 2Y3 35 14 36 13 3A0 3Y0 33 3A2 3Y2 16 3D 3 35 14 3A1 3A3 3Y3 17 3Y1 32 33 16 3A2 3Y2 30 4A0 4Y0 19 32 17 3A3 20 3Y3 29 4A1 4Y1 30 19 4A0 4A2 4Y2 4D 4 4Y0 27 22 29 20 26 4A3 4Y3 4A1 4Y1 23 27 22 2OE 4OE 4A2 4Y2 26 23 4A3 4Y3 48 24 001aaa360 001aaa358 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 47 2 36 13 1A0 1Y0 3A0 3Y0 46 3 35 14 1A1 3A1 1Y1 3Y1 44 5 33 16 1A2 1Y2 3A2 3Y2 43 6 32 17 1A3 1Y3 3A3 3Y3 1 25 1OE 3OE 41 8 30 19 2A0 2Y0 4A0 4Y0 40 9 29 20 2A1 4A1 2Y1 4Y1 38 11 27 22 2A2 2Y2 4A2 4Y2 37 12 26 23 2A3 2Y3 4A3 4Y3 48 24 2OE 4OE 001aaa359 Fig. 3. Logic diagram 74LVC16241A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 5 26 April 2019 2 / 12