74LVC240APW,118 Nexperia

74LVC240A Octal buffer/line driver with 5 V tolerant inputs/outputs inverting 3-state Rev. 9 6 May 2021 Product data sheet 1. General description The 74LVC240A is an 8-bit inverting buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 to 3.6 V CMOS low power consumption Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC240AD -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC240APW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVC240ABQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74LVC240A Octal buffer/line driver with 5 V tolerant inputs/outputs inverting 3-state 4. Functional diagram 2 1A0 1Y0 18 4 1A1 1Y1 16 6 1A2 1Y2 14 8 1A3 1Y3 12 1 EN 1 1OE 2 18 4 16 2 1A0 1Y0 18 2A0 2Y0 17 3 6 14 17 2A0 2Y0 3 8 12 15 2A1 2Y1 5 4 1A1 1Y1 16 15 2A1 2Y1 5 19 EN 2A2 13 2Y2 7 6 1Y2 14 1A2 13 2A2 2Y2 7 11 9 2A3 11 2Y3 9 8 12 1A3 1Y3 13 7 11 2Y3 9 2A3 5 15 2OE 19 3 1OE 17 1 19 2OE mgu779 mgu778 mgu780 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Functional diagram 74LVC240A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 6 May 2021 2 / 14