74LVC2G06GV-Q100H Nexperia

74LVC2G06-Q100 Inverters with open-drain outputs Rev. 2 13 December 2016 Product data sheet 1. General description The 74LVC2G06-Q100 provides two inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options74LVC2G06-Q100 Nexperia Inverters with open-drain outputs 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G06GW-Q100 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC2G06GV-Q100 40 C to +125 C TSOP6 plastic surface-mounted package (TSOP6) 6 leads SOT457 4. Marking Table 2. Marking 1 Type number Marking code 74LVC2G06GW-Q100 V6 74LVC2G06GV-Q100 V06 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram < < < *1 QE P E PQ D PQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one driver) 6. Pinning information 6.1 Pinning 9& * 4 / < *1 9 < DDD Fig 4. Pin configuration SOT363 and SOT457 74LVC2G06 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 13 December 2016 2 of 13 && < <