74LVC2G3157DP-Q10J Nexperia

74LVC2G3157-Q100 Dual 10 single-pole double-throw analog switch Rev. 2 12 May 2021 Product data sheet 1. General description The 74LVC2G3157-Q100 is a dual low-ohmic single-pole double-throw analog switch suitable for use as an analog or digital 2:1 multiplexer/demultiplexer. Each switch has a digital select input (nS), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). Schmitt trigger action at the select inputs makes the circuit tolerant of slower input rise and fall times across the entire V range from 1.65 V to 5.5 V. CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 10.4 (typical) at V = 2.7 V CC 7.8 (typical) at V = 3.3 V CC 6.2 (typical) at V = 5 V CC Switch current capability of 32 mA Break-before-make switching High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance exceeds 100 mA per JESD 78 Class II ESD protection: MIL-STD-883, method 3015 exceeds 2 kV HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV MM JESD22-A115-C exceeds 200 V (C = 200 pF R = 0 ) Select input accepts voltages up to 5.5 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G3157DP-Q100 -40 C to +125 C TSSOP10 plastic thin shrink small outline package SOT552-1 10 leads body width 3 mmNexperia 74LVC2G3157-Q100 Dual 10 single-pole double-throw analog switch 4. Marking Table 2. Marking codes Type number Marking code 1 74LVC2G3157DP-Q100 YJ 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y1 S Z 1Y0 2Y0 1S 2S 1Z 2Z Y0 1Y1 2Y1 001aaj085 001aac355 Fig. 1. Logic symbol Fig. 2. Logic diagram (one switch) 6. Pinning information 6.1. Pinning 74LVC2G3157 1S 1 10 1Z 1Y1 2 9 1Y0 GND 3 8 V CC 2Y1 4 7 2Y0 2S 5 6 2Z aaa-020231 Fig. 3. Pin configuration SOT552-1 (TSSOP10) 74LVC2G3157 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 12 May 2021 2 / 18