74LVC3G17DC-Q100H Nexperia

74LVC3G17-Q100 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 4 26 August 2021 Product data sheet 1. General description The 74LVC3G17-Q100 is a triple buffer with Schmitt-trigger inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity 24 mA output drive (V = 3.0 V) CC CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standards JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Applications Wave and pulse shapers for highly noisy environmentsNexperia 74LVC3G17-Q100 Triple non-inverting Schmitt trigger with 5 V tolerant input 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3G17DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74LVC3G17DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 5. Marking Table 2. Marking codes Type number Marking code 1 74LVC3G17DP-Q100 V17 74LVC3G17DC-Q100 V17 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 1A 1Y 3Y 3A 2A 2Y A Y 001aah860 001aah861 001aab109 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 7. Pinning information 7.1. Pinning 74LVC3G17-Q100 1A 1 8 V CC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y aaa-012620 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC3G17 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 26 August 2021 2 / 12