74LVC4066PW,112 Nexperia

74LVC4066 Quad bilateral switch Rev. 6 26 March 2020 Product data sheet 1. General description The 74LVC4066 is a high-speed Si-gate CMOS device. The 74LVC4066 provides four single pole, single-throw analog switch functions. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise and fall times across the entire V range from 1.65 V to 5.5 V. CC 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 (typical) at V = 2.7 V CC 6.5 (typical) at V = 3.3 V CC 6 (typical) at V = 5 V CC Switch current capability of 32 mA High noise immunity CMOS low-power consumption Direct interface TTL-levels Latch-up performance exceeds 250 mA ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Enable inputs accept voltages up to 5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC4066D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC4066PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC4066BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC4066 Quad bilateral switch 4. Functional diagram 1 1Y 1Z 2 1 2 1 1 13 X1 13 1E 1 2 13 4 3 4 2Y 2Z 3 1 1 4 3 5 X1 5 2E 5 8 9 8 3Y 3Z 9 1 1 8 9 6 X1 6 6 3E 11 10 11 10 1 1 11 4Y 4Z 10 12 12 X1 12 4E (a) (b) mnb111 mnb112 Fig. 1. Logic symbol Fig. 2. Logic symbol (IEEE/IEC) nZ nY nE V CC mna658 Fig. 3. Logic diagram (one switch) 5. Pinning information 5.1. Pinning terminal 1 index area 2 13 1Z 1E 2Z 3 12 4E 1Y 1 14 V CC 2Y 4 4066 11 4Y 1Z 2 13 1E (1) 2E 5 10 4Z GND 2Z 3 12 4E 3E 6 9 3Z 2Y 4 4066 11 4Y 2E 5 10 4Z 001aad118 Transparent top view 3E 6 9 3Z (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case 001aad117 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration for SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration for SOT762-1 (DHVQFN14) 74LVC4066 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 26 March 2020 2 / 20 GND 7 1 1Y 3Y 8 14 V CC