74LVC594APW-Q100J Nexperia

74LVC594A-Q100 8-bit shift register with output register Rev. 3 3 September 2020 Product data sheet 1. General description The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The device features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. A LOW level on one of the two register reset pins (SHR and STR) will clear the corresponding register. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications Serial-to-parallel data conversion Remote control holding registerNexperia 74LVC594A-Q100 8-bit shift register with output register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC594AD-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC594APW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74LVC594ABQ-Q100 -40 C to +125 C DHVQFN16 plastic dual in-line compatible SOT763-1 thermal enhanced very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 5. Functional diagram SHCP STCP 11 12 Q7S 9 14 DS 15 Q0 11 SHCP 8-STAGE SHIFT REGISTER 1 Q1 10 SHR Q2 2 9 Q7S DS 14 3 Q3 4 Q4 12 STCP 5 Q5 8-BIT STORAGE REGISTER 13 STR 6 Q6 7 Q7 15 1 2 3 4 5 6 7 10 13 SHR STR mbc319 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc320 Fig. 1. Logic symbol Fig. 2. Functional diagram 74LVC594A Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 3 September 2020 2 / 18