74LVC8T245-Q100 74LVCH8T245-Q100 8-bit dual supply translating transceiver 3-state Rev. 2 22 September 2020 Product data sheet 1. General description The 74LVC8T245-Q100 74LVCH8T245-Q100 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (V and V ). Both V and V can be supplied at any voltage between 1.2 V and CC(A) CC(B) CC(A) CC(B) 5.5 V. This flexibility makes the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to V and pins CC(A) Bn are referenced to V . A HIGH on DIR allows transmission from An to Bn and a LOW on CC(B) DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both A port and B CC(A) CC(B) port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH8T245-Q100 holds unused or floating data inputs at a valid logic level. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range: V : 1.2 V to 5.5 V CC(A) V : 1.2 V to 5.5 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: MIL-STD-883, method 3015 Class 3A exceeds 4000 V HBM JESD22-A114F Class 3A exceeds 4000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Maximum data rates: 420 Mbps (3.3 V to 5.0 V translation) 210 Mbps (translate to 3.3 V)) 140 Mbps (translate to 2.5 V) 75 Mbps (translate to 1.8 V) 60 Mbps (translate to 1.5 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78B Class II 24 mA output drive (V = 3.0 V) CCNexperia 74LVC8T245-Q100 74LVCH8T245-Q100 8-bit dual supply translating transceiver 3-state Inputs accept voltages up to 5.5 V Low power consumption: 30 A maximum I CC I circuitry provides partial Power-down mode operation OFF DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC8T245PW-Q100 -40 C to +125 C TSSOP24 plastic thin shrink small outline package SOT355-1 24 leads body width 4.4 mm 74LVCH8T245PW-Q100 74LVC8T245BQ-Q100 -40 C to +125 C DHVQFN24 plastic dual in-line compatible SOT815-1 thermal enhanced very thin quad 74LVCH8T245BQ-Q100 flat package no leads 24 terminals body 3.5 5.5 0.85 mm 4. Functional diagram B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14 V V CC(A) CC(B) 22 OE 2 DIR 3 4 5 6 7 8 9 10 A1 A2 A3 A4 A5 A6 A7 A8 001aai472 Fig. 1. Logic symbol DIR OE A1 B1 V V CC(A) CC(B) to other seven channels 001aai473 Fig. 2. Logic diagram (one channel) 74LVC LVCH8T245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 22 September 2020 2 / 26