74LVT126D,112 Nexperia

74LVT126 3.3 V quad buffer 3-state Rev. 6 27 July 2021 Product data sheet 1. General description The 74LVT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This device is fully specified for partial power down applications using I . The I circuitry disables OFF OFF the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Quad bus interface 3-state buffers Wide supply voltage range from 2.7 to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Output capability: +64 mA and -32 mA Direct interface with TTL levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up 3-state I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: MIL STD 883 method 3015: exceeds 2000 V MM: exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVT126D -40 C to +85 C SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 74LVT126PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVT126BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVT126 3.3 V quad buffer 3-state 4. Functional diagram 2 2 1A 1Y 3 1 3 1 1 1OE EN1 5 2A 2Y 6 5 6 4 2OE 4 9 3A 3Y 8 9 8 10 3OE 10 12 12 4A 4Y 11 11 13 13 4OE 001aac482 001aac483 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74LVT126 1OE 1 14 V CC 74LVT126 1A 2 13 4OE 1OE 1 14 V 1Y 3 12 4A CC 1A 2 13 4OE 2OE 4 11 4Y 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE 2A 5 10 3OE 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y aaa-026920 aaa-026921 Fig. 3. Pin configuration SOT108-1 (SO14) Fig. 4. Pin configuration SOT402-1 (TSSOP14) 74LVT126 terminal 1 index area 1A 2 13 4OE 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE (1) GND 6 9 2Y 3A aaa-026922 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74LVT126 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 27 July 2021 2 / 13 GND 7 1 1OE 3Y 8 14 V CC