74LVT240 3.3 V Octal inverting buffer/line driver 3-state Rev. 4 28 July 2021 Product data sheet 1. General description The 74LVT240 is an 8-bit inverting buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. 2. Features and benefits Octal bus interface 3-state buffers Wide supply voltage range from 2.7 to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Output capability: +64 mA and -32 mA Direct interface with TTL levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: MIL STD 883 method 3015: exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to 85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT240D -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVT240PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mmNexperia 74LVT240 3.3 V Octal inverting buffer/line driver 3-state 4. Functional diagram 1 EN 2 18 2 1A0 1Y0 18 4 16 11 2A0 2Y0 9 6 14 4 1A1 1Y1 16 8 12 13 2A1 2Y1 7 19 6 1A2 1Y2 14 EN 15 2A2 2Y2 5 11 9 8 1A3 1Y3 12 13 7 17 2A3 2Y3 3 15 5 17 3 1 1OE 19 2OE aaa-026569 aaa-026570 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74LVT240 74LVT240 1OE 1 20 V 1OE 1 20 V CC CC 1A0 2 19 2OE 1A0 2 19 2OE 2Y3 3 18 1Y0 2Y3 3 18 1Y0 1A1 4 17 2A3 1A1 4 17 2A3 2Y2 5 16 1Y1 2Y2 5 16 1Y1 1A2 6 15 2A2 1A2 6 15 2A2 2Y1 7 14 1Y2 2Y1 7 14 1Y2 1A3 8 13 2A1 1A3 8 13 2A1 2Y0 9 12 1Y3 2Y0 9 12 1Y3 GND 10 11 2A0 GND 10 11 2A0 aaa-026571 aaa-026572 Fig. 3. Pin configuration SOT163-1 (SO20) Fig. 4. Pin configuration SOT360-1 (TSSOP20) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 19 output enable input (active LOW) 1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input 2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 bus output GND 10 ground (0 V) 2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input 1Y0, 1Y1, 1Y2, 1Y3 18, 16, 14, 12 bus output V 20 supply voltage CC 74LVT240 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 28 July 2021 2 / 12