74LVT240DB,118 Nexperia

74LVT240 3.3 V Octal inverting buffer/line driver; 3-state Rev. 3 10 April 2017 Product data sheet 1 General description The 74LVT240 is a high-performance BiCMOS product designed for V operation at CC 3.3 V. This device is an octal inverting buffer that is ideal for driving bus lines. The device features two output enable pins (1OE, 2OE), each controlling four of the 3-State outputs. 2 Features and benefits Octal bus interface 3-state buffers Output capability: +64 mA and -32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection JESD78 Class II exceeds 500 mA ESD protection: MIL STD 883 method 3015: exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT240D -40 C to +85 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74LVT240DB -40 C to +85 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74LVT240PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package; SOT360-1 20 leads; body width 4.4 mmNexperia 74LVT240 3.3 V Octal inverting buffer/line driver; 3-state 4 Functional diagram 1 EN 18 2 2 1A0 1Y0 18 16 4 11 2A0 2Y0 9 14 6 12 4 1A1 1Y1 16 8 13 2A1 2Y1 7 19 6 1A2 1Y2 14 EN 15 2A2 2Y2 5 9 11 8 1A3 1Y3 12 7 13 17 2A3 2Y3 3 5 15 3 17 1 1OE 19 2OE aaa-026569 aaa-026570 Figure 1. Logic symbol Figure 2. IEC logic symbol 5 Pinning information 5.1 Pinning 74LVT240 74LVT240 1OE 1 20 V 1OE 1 20 V CC CC 1A0 2 19 2OE 1A0 2 19 2OE 2Y3 3 18 1Y0 2Y3 3 18 1Y0 1A1 4 17 2A3 1A1 4 17 2A3 2Y2 5 16 1Y1 2Y2 5 16 1Y1 1A2 6 15 2A2 1A2 6 15 2A2 2Y1 7 14 1Y2 2Y1 7 14 1Y2 1A3 8 13 2A1 1A3 8 13 2A1 2Y0 9 12 1Y3 2Y0 9 12 1Y3 GND 10 11 2A0 GND 10 11 2A0 aaa-026571 aaa-026572 Figure 3. Pin configuration for SO20 Figure 4. Pin configuration for (T)SSOP20 74LVT240 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 3 10 April 2017 2 / 15