74VHC125PW,118 Nexperia

74VHC125 74VHCT125 Quad buffer/line driver 3-state Rev. 3 8 April 2020 Product data sheet 1. General description The 74VHC125 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC125 74VHCT125 are identical to the 74VHC126 74VHCT126 but have active LOW enable inputs. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC Input levels: The 74VHC125 operates with CMOS logic levels The 74VHCT125 operates with TTL logic levels ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC125D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74VHCT125D 74VHC125PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74VHCT125PW 74VHC125BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals 74VHCT125BQ body 2.5 3 0.85 mmNexperia 74VHC125 74VHCT125 Quad buffer/line driver 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 4 2OE 6 4 9 3A 3Y 8 9 8 3OE 10 10 4A 4Y nA nY 12 11 12 11 4OE 13 13 nOE mna228 mna229 mna227 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one buffer) 5. Pinning information 5.1. Pinning 74VHC125 74VHCT125 terminal 1 index area 2 13 1A 4OE 1Y 3 12 4A 74VHC125 74VHCT125 2OE 4 11 4Y 2A 5 (1) 10 3OE GND 1 14 1OE V CC 2Y 6 9 3A 2 13 1A 4OE 1Y 3 12 4A 4 11 2OE 4Y 001aak045 5 10 2A 3OE Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or 7 GND 8 3Y mechanical requirement to solder the pad. In case 001aak044 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74VHC VHCT125 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 8 April 2020 2 / 14 GND 7 1 1OE 3Y 8 14 V CC