74VHC126-Q100 74VHCT126-Q100 Quad buffer/line driver 3-state Rev. 2 6 April 2020 Product data sheet 1. General description The 74VHC126-Q100 74VHCT126-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC126-Q100 74VHCT126-Q100 provide four non-inverting buffer/line drivers with 3-state outputs. The output enable input (nOE) controls the 3-state outputs (nY). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Balanced propagation delays All inputs have Schmitt-trigger action Inputs accept voltages higher than V CC Input levels: The 74VHC126-Q100 operates with CMOS input level The 74VHCT126-Q100 operates with TTL input level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC126D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74VHCT126D-Q100 74VHC126PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74VHCT126PW-Q100 74VHC126BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74VHCT126BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74VHC126-Q100 74VHCT126-Q100 Quad buffer/line driver 3-state 4. Functional diagram 2 1A 1Y 3 2 1 3 1 1OE 1 EN1 2A 2Y 6 5 5 6 4 2OE 4 9 3A 3Y 8 9 8 3OE 10 10 nY nA 4A 4Y 12 11 12 11 13 4OE 13 nOE mna235 mna234 mna236 Fig. 1. Functional diagram Fig. 2. Logic symbol Fig. 3. IEC logic symbol 5. Pinning information 5.1. Pinning 74VHC126-Q100 74VHCT126-Q100 terminal 1 index area 74VHC126-Q100 74VHCT126-Q100 1A 2 13 4OE 3 12 1 14 1Y 4A 1OE V CC 2OE 4 11 4Y 1A 2 13 4OE 2A 5 10 3OE (1) GND 1Y 3 12 4A 2Y 6 9 3A 2OE 4 11 4Y 2A 5 10 3OE aaa-009731 Transparent top view 6 9 2Y 3A (1) This is not a ground pin. There is no electrical or GND 7 8 3Y mechanical requirement to solder the pad. In case aaa-009730 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 output enable input (active HIGH) 1A, 2A, 3A, 4A 2, 5, 9, 12 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74VHC VHCT126 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 6 April 2020 2 / 14 GND 7 1 1OE 3Y 8 14 V CC