74VHC02 74VHCT02 Quad 2-input NOR gate Rev. 2 15 April 2020 Product data sheet 1. General description The 74VHC02 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC02 74VHCT02 provide a quad 2-input NOR function. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accept voltages higher than V CC Input levels: The 74VHC02 operates with CMOS input level The 74VHCT02 operates with TTL input level ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC02D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74VHCT02D 74VHC02PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74VHCT02PW 74VHC02BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals 74VHCT02BQ body 2.5 3 0.85 mmNexperia 74VHC02 74VHCT02 Quad 2-input NOR gate 4. Functional diagram 2 2 1A 1 1 1Y 1 3 3 1B 5 5 2A 1 2Y 4 4 6 6 2B 8 3A 8 3Y 10 1 10 9 3B 9 A 11 4A 11 4Y 13 Y 1 12 4B 13 12 B mna216 001aah084 mna215 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74VHC02 74VHCT02 terminal 1 index area 1A 2 13 4Y 3 12 1B 4B 74VHC02 74VHCT02 2Y 4 11 4A 2A 5 10 3Y (1) GND 1Y 1 14 V CC 2B 6 9 3B 1A 2 13 4Y 1B 3 12 4B 2Y 4 11 4A 001aak053 2A 5 10 3Y Transparent top view 2B 6 9 3B (1) This is not a ground pin. There is no electrical or GND 7 8 3A mechanical requirement to solder the pad. In case 001aak052 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1Y, 2Y, 3Y, 4Y 1, 4, 10, 13 data output 1A, 2A, 3A, 4A 2, 5, 8, 11 data input 1B, 2B, 3B, 4B 3, 6, 9, 12 data input GND 7 ground (0 V) V 14 supply voltage CC 74VHC VHCT02 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 15 April 2020 2 / 12 GND 7 1 1Y 3A 8 14 V CC