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This literature is subject to all applicable copyright laws and is not for resale in any manner.74VHC27 Triple 3-Input NOR Gate December 2007 74VHC27 Triple 3-Input NOR Gate Features General Description High speed: t = 4.1ns (typ) at T = 25C The VHC27 is an advanced high speed CMOS 3-Input PD A NOR Gate fabricated with silicon gate CMOS technol- Low power dissipation: I = 2A (max) at T = 25C CC A ogy. It achieves the high-speed operation similar to High noise immunity: V = V = 28% V (min.) NIH NIL CC equivalent Bipolar Schottky TTL while maintaining the Power down protection is provided on all inputs CMOS low power dissipation. Low noise: V = 0.8V (max.) OLP The internal circuit is composed of 3 stages including Pin and function compatible with 74HC27 buffer output, which provide high noise immunity and stable output. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as bat- tery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Package Order Number Number Package Description 74VHC27M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC27SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC27MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1994 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC27 Rev. 1.4.0