HEF4027B
Dual JK flip-flop
Rev. 10 21 March 2016 Product data sheet
1. General description
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct
(SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is
LOW, and transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and
override the J, K, and CP inputs. The outputs are buffered for best system performance.
Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended V power supply range of 3 V to 15 V referenced to V
DD SS
(usually ground). Unused inputs must be connected to V , V , or another input.
DD SS
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Registers
Counters
Control circuits
4. Ordering information
Table 1. Ordering information
T from 40 C to +85 C.
amb
Type number Package
Name Description Version
HEF4027BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1HEF4027B
Nexperia
Dual JK flip-flop
5. Functional diagram
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Fig 1. Functional diagram
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Fig 2. Logic diagram of one flip-flop
HEF4027B All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet Rev. 10 21 March 2016 2 of 13
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