NBSG53A 2.5 V/3.3 VSiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS* NBSG53A V R SEL OLS CC Exposed Pad 16 15 14 13 (EP) VTCLK 1 12 V EE CLK 2 11 Q NBSG53A CLK Q 3 10 VTCLK V 4 9 CC 56 7 8 VTD D D VTD Figure 1. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTCLK Internal 50 Termination Pin. See Table 4. 2 CLK ECL, CML, Inverted Differential Input. LVCMOS, LVDS, LVTTL Input 3 CLK ECL, CML, Noninverted Differential Input. LVCMOS, LVDS, LVTTL Input 4 VTCLK Internal 50 Termination Pin. See Table 4. 5 VTD Internal 50 termination pin. See Table 4. 6 D ECL, CML, Inverted Differential Input. LVCMOS, LVDS, LVTTL Input 7 D ECL, CML, Noninverted Differential Input. LVCMOS, LVDS, LVTTL Input 8 VTD Internal 50 Termination Pin. See Table 4. 9,16 V Positive Supply Voltage CC 10 Q RSECL Output NonInverted Differential Output. Typically Terminated with 50 Resistor to V = V 2 V. TT CC 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V = V 2 V. TT CC 12 V Negative Supply Voltage EE 13 OLS* Input Input Pin for the Output Level Select (OLS). See Table 2. 14 SEL LVECL, LVCMOS, Select Logic Input. Internal 75 k to V . EE LVTTL Input 15 R LVECL, LVCMOS, Reset D Flip-Flop. Internal 75 k to V . EE LVTTL Input EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on CC EE package bottom (see case drawing) must be attached to a heat-sinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. 3. When an output level of 400 mV is desired and V V > 3.0 V, 2 k resistor should be connected from OLS pin to V . CC EE EE