NBSG86A 2.5V/3.3VSiGe Differential Smart Gate with Output Level Select The NBSG86A is a multifunction differential Logic Gate which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 www.onsemi.com MUX. This device is part of the GigaComm family of high performance Silicon Germanium products. The device is housed in a MARKING 3 x 3 mm 16 pin QFN package. DIAGRAM* Differential inputs incorporate internal 50 termination resistors 16 and accept NECL (Negative ECL), PECL (Positive ECL), 1 SG LVCMOS/LVTTL, CML, or LVDS. The Output Level Select (OLS) 1 86A input is used to program the peaktopeak output amplitude between ALYW QFN16 0 and 800 mV in five discrete steps. MN SUFFIX The NBSG86A employs input default circuitry so that under open CASE 485G input conditions (D , D , VTD , VTD VTSEL) the outputs of the x x x x, device will remain stable. A = Assembly Location L = Wafer Lot Features Y = Year Maximum Input Clock Frequency > 8 GHz Typical W = Work Week = PbFree Package Maximum Input Data Rate > 8 Gb/s Typical (Note: Microdot may be in either location) 165 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times *For additional marking information, refer to Application Note AND8002/D. Selectable Swing PECL Output with Operating Range: V = 2.375 V to 3.465 V with V = 0 V CC EE Selectable Swing NECL Output with NECL Inputs with ORDERING INFORMATION Operating Range: V = 0 V with V = 2.375 V to 3.465 V CC EE See detailed ordering and shipping information on page 16 of Selectable Output Level (0 V, 200 mV, 400 mV, this data sheet. 600 mV, or 800 mV PeaktoPeak Output) 50 Internal Input Termination Resistors This is a PbFree Device Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: January, 2018 Rev. 20 NBSG86A/DNBSG86A VTD0 D0 D0 VTD0 Exposed Pad 16 15 14 13 (EP) OLS 1 12 V EE SEL 2 11 Q NBSG86A SEL Q 3 10 VTSEL V 4 9 CC 56 7 8 VTD1 D1 D1 VTD1 Figure 1. QFN16 Pinout (Top View) Table 1. Pin Description Pin Name I/O Description 1 OLS Input Input Pin for the Output Level Select (OLS). See Table 2. (Note 3) 2 SEL ECL, CML, LVCMOS, Inverted Differential Select Logic Input. LVDS, LVTTL Input 3 SEL ECL, CML, LVCMOS, Noninverted Differential Select Logic Input. LVDS, LVTTL Input 4 VTSEL Common Internal 50 Termination Pin for SEL/SEL. See Table 7. (Note 1) 5 VTD1 Internal 50 termination pin. See Table 7. (Note 1) 6 D1 ECL, CML, LVCMOS, Noninverted Differential Input 1. Internal 75 k to V . EE LVDS, LVTTL Input 7 D1 ECL, CML, LVCMOS, Inverted Differential Input 1. Internal 75 k to V and 36.5 k to V . EE CC LVDS, LVTTL Input 8 VTD1 Internal 50 Termination Pin. See Table 7. (Note 1) 9 V Positive Supply Voltage (Note 2) CC 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V = V TT CC 2 V. 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V = V 2 V TT CC 12 V Negative Supply Voltage (Note 2) EE 13 VTD0 Internal 50 Termination Pin. See Table 7. (Note 1) 14 D0 ECL, CML, LVCMOS, Inverted Differential Input 0. Internal 75 k to V and 36.5 k to V . EE CC LVDS, LVTTL Input 15 D0 ECL, CML, LVCMOS, Noninverted Differential Input 0. Internal 75 k to V . EE LVDS, LVTTL Input 16 VTD0 Internal 50 Termination Pin. See Table 7. (Note 1) EP The Exposed Pad (EP) and the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage, or left open, and if no signal is applied then the device will be susceptible to selfoscillation. 2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. CC EE 3. When an output level of 400 mV is desired and V V > 3.0 V, 2 k resistor should be connected from OLS pin to V . CC EE EE www.onsemi.com 2