HEF4020BT-Q100J Nexperia

HEF4020B-Q100 14-stage binary counter Rev. 3 7 December 2021 Product data sheet 1. General description The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . DD This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 3) Specified from -40 C to +85 C Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity High speed operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4020BT-Q100 -40 C to +85 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mmNexperia HEF4020B-Q100 14-stage binary counter 4. Functional diagram 10 CP T 14-STAGE COUNTER 11 MR C D 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad722 Fig. 1. Functional diagram CTR14 Q0 9 0 9 + 10 Q3 7 7 11 CT Q4 5 5 Q5 4 4 10 CP Q6 6 6 Q7 13 13 CT Q8 12 12 Q9 14 14 11 MR Q10 15 15 Q11 1 1 Q12 2 2 Q13 3 13 3 001aad723 001aad724 Fig. 2. Logic symbol Fig. 3. IEC Logic symbol Q Q Q Q Q Q Q FF FF FF FF FF FF FF 0 1 2 3 4 5 6 T T T T T T T CP Q Q Q Q Q Q Q RD RD RD RD RD RD RD MR Q0 Q3 Q4 Q5 Q6 Q Q Q Q Q Q Q FF FF FF FF FF FF FF 7 8 9 10 11 12 13 T T T T T T T Q Q Q Q Q Q Q RD RD RD RD RD RD RD Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad725 Fig. 4. Logic diagram HEF4020B Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 7 December 2021 2 / 11